Q-CTRL Wins 2023 Startup Daily’s ‘Best in Tech’ Award for Most Innovative Startup
September 6, 2023
We’re excited to be returning supporters of the Superconducting Qubits and Algorithms (SQA) Conference and will look forward to meeting you in Munich, Germany from August 29 to September 1!
From near-term algorithms and applications to quantum error correction and suppression, our expert team of quantum control scientists and engineers will present the latest cutting-edge research driving innovation in quantum computing.
Mark your diaries with the following sessions!
Benchmarking and enabling software
Discover how you can use a new approach to quantum verification in order to accurately predict the best way to run your algorithm.
Near-term algorithms, applications, and co-design
Learn how we are advancing the state of the art in quantum applications through application modules optimized for execution on real hardware combined with the state-of-the-art in error suppression technology.
Quantum error correction and mitigation
Hear how AI agents can design a whole new “machine language” for quantum computers to implement algorithms with huge reductions in error - all with no human intervention.
Whether you are an end user seeking to understand how to gain a strategic advantage with quantum computing, or leading a high-pace quantum R&D effort, we have solutions to help.
We look forward to discussing your needs, and we hope that you join us for a special celebration at the conference dinner. Prost! 🍻
A physics-inspired machine learning approach for circuit layout selection on noisy quantum devices
Poster Session Thursday:
Noise in current quantum devices is inhomogeneous in both space and time. Gate fidelities, qubit T1 lifetimes, and other parameters vary across the device and exhibit fluctuations on the scale of hours. These inhomogeneities lead to significant variability in the empirical fidelity of an executed circuit based on the layout, the mapping of qubits in the circuit to physical qubits in the device. Although a compiled circuit will typically yield many valid layouts, in practical applications only a single layout will be used. The problem of layout selection is then to reliably predict the best performing one. Layout selection is an important component of the circuit compilation and error suppression pipeline for noisy intermediate scale quantum devices. In this work, we introduce a physics-inspired machine learning approach for layout selection that utilizes both device calibration data as well as training data from previously executed circuits to learn a score function that can be used to rank different layouts according to their expected performance. We evaluate our approach across multiple devices and quantum algorithms, and find consistent improvements over existing methods. Averaged over many circuits, our predicted best layout is in the top-2 best actual layouts more than 50% of the time. Moreover, the predicted layouts are quite close to optimal, achieving 97.5% of the fidelity of the best performing layout. An article summarizing this work is in preparation and is slated to appear as a preprint shortly.
Algorithm co-design for field-testing the path to advantage
Poster Session Wednesday:
To help end users to appreciate both the current status and the potential future impact of quantum computing, providing practical-scale solutions that leverage quantum resources is a powerful demonstration. These demonstrations ideally satisfy three criteria: they feature (1) a current quantum computation at non-trivial scale (though presently inferior to a classical alternative in solution quality or run-time), (2) a smooth scaling approach within the solution methodology such that the quantum computation can measurably scale towards a target threshold for potential quantum advantage, and (3) algorithm design that minimizes the most challenging resources for a given hardware (e.g. circuit depth or connectivity). As an illustration, we outline a hybrid scheduling and routing optimisation algorithm applicable to freight and public transport. Our algorithm provides solutions for full-scale use-cases and features meeting the desiderata above: a current high-performing quantum routing optimisation sub-routine for ~6 vehicles on several available routes; a problem decomposition method that offers smooth scaling of the number of vehicles towards the classically-challenging threshold at ~100 vehicles; and resource requirements of only sparse two-qubit connectivity outside local qubit clusters (desirable for superconducting qubits) and circuit duration less than 1ms for classically-challenging problems (i.e. within challenging but achievable T1 limits on superconducting devices). Additionally, our method is designed to offer quantum enhancement of a classical solver, which is a promising avenue for near-term advantage. We highlight the impact of our error-reducing infrastructure software, which increases current high-quality solution size (2X larger than direct hardware deployment), provides >6X improvement in time-to-solution, and reduces the device T1 limit required for large scale problems by ~20%.
Vehicle routing optimization using near-term superconducting hardware
Poster Session Thursday:
Vehicle routing is a ubiquitous combinatorial optimisation problem in logistics, and is suitable for near-term quantum optimisation using QAOA. However, the problem size that can be executed on real hardware is limited in scale by both qubit count and noise. Our novel problem representation for capacitated vehicle routing provides an exponential reduction in required qubits with respect to target routing locations. Hardware errors can then be mitigated to some extent through reduced circuit size. We design a custom component of the QAOA circuit to incorporate problem constraints, having an exponential circuit depth reduction over standard methods. However, the number of two-qubit gates scales polynomially with the problem size in the cost circuit; this is compounded by the limited connectivity of superconducting devices, requiring the use of SWAP gates. We discuss approaches to the question of how to further reduce the circuit scaling without compromising algorithm performance. Our error reduction workflow leverages QAOA implementation enhancements that include the classical control workflow and hardware-efficient compilation. We present vehicle optimisation results using superconducting hardware where our workflow reduces errors by over 20X, as well as hardware milestones for performance at relevant scales for classically-challenging problems.
Algorithmic performance improvement with hardware efficient gates
Poster Session Wednesday:
Useful quantum algorithms which utilize only the standard entangling gates like CNOT, iSWAP, etc. fail to produce meaningful results on the NISQ devices. Superconducting circuits provide a diverse variety of native multi-qubit interactions depending on the device architecture and gate-drive scheme. The calibration of high fidelity continuously parameterized gates and the construction of an efficient circuit compilation scheme that leverages the richer gate set are open problems. In this talk we present a procedure that efficiently optimizes a small set of system wide entangling gates, which in turn, can be used online to generate arbitrary angles gates. Our approach requires minimal calibration resources and produces short and high-fidelity parametric gates. To ensure these gates are utilized properly, we built a specialized compilation pass that automatically finds and replaces optimizable patterns in quantum circuits. We demonstrate our approach in two key quantum algorithms- QAOA and syndrome detection in a QEC code. For a 7-qubit MaxCut QAOA, the default circuit execution on a cloud-accessible quantum computer fails to give the correct bit string as the mode of the output distribution while our approach achieves the correct answer with 99% probability. For syndrome detection, we experimentally demonstrate 40% reduction in the duration of the parity check operation. These results signify the importance of both the hardware efficient gates and deterministic error suppression for making quantum devices useful.
September 6, 2023
September 5, 2023